# cpu-internals: a condensed Intel SDM notebook for system programmers > This repository is a set of personal notes taken from the Intel Software Developer's Manual, covering modes of operation, memory models, paging, interrupt handling, cache control and the VMX chapters for hypervisor work. It is a reading aid with no code to build, and it is incomplete by design. **ayoubfaouzi/cpu-internals** — Intel / AMD CPU Internals - Repository: https://github.com/ayoubfaouzi/cpu-internals - Stars: 1,214 · Forks: 190 - Language: C - License: not declared - Published: 2026-10-19 · Updated: 2026-10-19 · Language: en - Canonical page: https://hysenlabs.com/projects/ayoubfaouzi-cpu-internals ## One person's condensed notes from the Intel SDM The repository states its own scope in the first line. These notes are taken from Intel SDM, and the author describes them as a short or resumed version of some parts of the manuals that he found worth looking at while learning about system programming, OS internals or virtualization. That framing matters, because it tells you what kind of artefact this is. It is a study notebook, not a specification and not a tutorial with a worked example. The value is in the selection and the compression: the manual is thousands of pages, and this keeps the chapters that a systems programmer actually reads. The primary language of the repository is listed as C, which is a reasonable signal about the audience even though the notes themselves are prose. The repository topics give a clearer picture: ept, hardware-virtualization, hypervisor, paging, segmentation and vt-x. Those six tags are effectively a summary of the contents, and they tell you the material is oriented towards writing a hypervisor or an operating system rather than towards application level performance work. There is also a homepage of none and no GitHub releases, so this is a repository you read rather than a package you install. The last push was on 2026-06-24 and the repository is not archived, so the notes are still being worked on, which also means they may change without notice. ## The table of contents is the real map of the project The README opens with a contents list organised by manual volume, and reading it tells you exactly what has been covered and what has not. From Volume 1 Basic Architecture there are two chapters: Chapter 3 Basic Execution Environment, and Chapter 6 Procedure Calls, Interrupts, and Exceptions. From Volume 2 Instruction Set Reference there is one, Chapter 6 Safer Mode Extensions Reference. From Volume 3 System Programming Guide there are twelve: Chapter 2 System Architecture Overview, Chapter 3 Protected Mode Memory Management, Chapter 4 Paging, Chapter 6 Interrupt and Exception Handling, Chapter 11 Memory Cache Control, Chapter 17 Debug, Branch Profile, TSC and Intel RDT Features, Chapter 22 Architecture Compatibility, Chapter 23 Introduction to Virtual Machine Extensions, Chapter 24 Virtual Machine Control Structures, Chapter 25 VMX Non-Root Operation, Chapter 28 VMX Support for Address Translation and Chapter 30 VMX Instruction Reference. Two observations follow. First, the selection is heavily weighted towards Volume 3, which is the system programming guide and the part of the manual that matters for a kernel or a hypervisor developer. Second, the virtualisation coverage is coherent as a sequence rather than a grab bag: an introduction to VMX, the control structures, non-root operation, address translation support and the instruction reference, in that order. That is the order you need them in when you build something on VT-x. The gaps are equally informative. Volume 3 chapters on things like the machine check architecture, processor thermal management, multi-processing and the instruction set reference chapters are not in the list. The notes cover a path, not the whole manual. ## Modes of operation and the three memory models The Chapter 3 material is the densest part of the visible notes, and it is where the guide earns its place for a reader who has been treating protected mode as a single concept. The modes are laid out one by one. Protected mode is the native state of the processor and includes the virtual-8086 feature for running real-mode 8086 software in a protected, multitasking environment. Real-address mode is the programming environment for the 8086, the processor is placed in it after power-up or reset, DOS runs in it, and it can switch to protected mode or SMM mode. System Management Mode implements platform specific functions such as power management and system security, and the processor enters it when an SMI is received from the APIC or when the external SMI pin is activated. Intel 64 adds IA-32e mode with two sub-modes: compatibility mode, which lets most legacy 16-bit and 32-bit applications run without recompilation under a 64-bit operating system, and long mode, which enables a 64-bit operating system to run applications written to access a 64-bit linear address space. In 64-bit mode the general purpose and SIMD registers extend from 8 to 16 and the GPRs are widened to 64 bits. The memory models are then separated from the modes, which is the part most write-ups blur together. Programs never address physical memory directly; they use one of three models. The flat model presents memory as a single continuous address space containing code, data and stacks. The segmented model presents memory as a group of independent segments, and a logical address (a far pointer) is a segment selector plus an offset producing a linear address, with up to 16,383 segments addressable, and the stated primary reason for using segmentation is to increase the reliability of programs and systems, since placing a stack in its own segment stops it from growing into the code or data space. The notes are explicit about which mode allows which model. Protected mode can use any of the three. Real-address mode supports only the real-address model. SMM switches to a separate address space, the system management RAM, addressed similarly to real mode. Compatibility mode observes the same memory model as 32-bit protected mode. And in 64-bit mode segmentation is generally but not completely disabled, the segment base of CS, DS, ES and SS is treated as zero so a linear address equals an effective address, and the segmented and real address modes are not available at all. ## Paging, PAE and PSE, in the notes' own terms The paging section of the visible notes is short, which reflects the condensed nature of the project rather than the complexity of the subject. The core statements are these. When paging is disabled, each linear address has a one-to-one correspondence with a physical address. When paging is enabled, the linear address space is divided into pages which are mapped to virtual memory, and the pages of virtual memory are then mapped as needed into physical memory. Paging is completely transparent to an application, and all the application sees is the linear address space. The two extensions named are the ones that matter for anything past 32-bit. Physical Address Extensions (PAE) support addressing a physical address space greater than 4 GB. Page Size Extensions (PSE) map a linear address to a physical address in 4-MB pages. It would be wrong to treat this section as a substitute for Chapter 4 of the manual, and the notes themselves do not pretend otherwise. What you get here is the mental model in a few lines: the application sees a linear address, the processor does the translation, and two extension mechanisms widen the address space. The details of the page table entry formats, the control registers, the TLB behaviour and the huge page variants are what Chapter 4 and the related VMX address translation material are for, and this project is a pointer to them rather than a replacement. That framing is the honest one for the whole repository. It is best read as an index with context attached, useful for deciding which manual chapter to read next and for remembering the shape of an argument once you have read it. ## VMX coverage, and the files that sit beside the notes The repository layout gives a sense of what else is in there beyond the README text. The top level contains README.md, a chapter-06-interrupt-and-exception-handling.md file, hardware.md, a VMCS-Layout.pdf, and the directories assets/, figures/, headers/ and manuals/. VMCS-Layout.pdf is the most interesting of these for a virtualisation reader. The Virtual Machine Control Structures are what a VMM writes to configure the hardware, so a layout reference sitting next to the notes is a working aid rather than background reading, and it is the kind of artefact that gets printed and pinned above a desk. The headers/ directory is consistent with the C primary language: a hypervisor needs the structure definitions to program against, and the manual presents them in prose and tables that are awkward to work from directly. The manuals/ and assets/ directories suggest the source material and the figures are vendored into the repository, and figures/ holds the images the notes embed, such as the memory model and basic execution environment diagrams. Vendoring manuals is also why the licence situation is not straightforward, and there is more on that below. Taken with the chapter list, the repository is coherent as a hypervisor preparation kit: architecture basics, memory management, interrupts, cache control, the debugging and TSC features, architecture compatibility, and then the VMX sequence from introduction through instruction reference, with the control structure layout and the headers as working material. ## What is missing, and why the alternative is the manual itself The gaps are significant enough that this project is best treated as a supplement. The visible README text stops partway through the basic program execution registers section, so the register description is incomplete in what is published. The interrupt and exception material appears both in the Volume 1 chapter 6 listing and in a separate top-level markdown file, and the second volume contribution is a single chapter on safer mode extensions, which is an unusual choice to summarise at all. There is no code to run, no build step, and no executable. The repository is not a library and does not appear to offer one, so the alternative is not another project but the source it condenses. The genuine comparison is between reading the Intel Software Developer's Manual directly and reading these notes first. The difference in approach is compression versus completeness, with a licensing consequence attached. The manual is authoritative and current with the silicon. These notes are a curated subset, arranged by someone else's judgement about what mattered, and they will drift out of date as the platform moves, as the repository's own git history shows with a last push on 2026-06-24 while the underlying volumes keep being revised. The strongest use is as a study index: work through the notes, then open the manual at the chapter the notes point to. The weakest use is to quote a line from these notes in a design document, because the citation chain ends at one person's paraphrase rather than at Intel's text. ## Licence, reuse, and what to check before you copy anything No licence is stated for this project, and the top level entries include a .gitignore and README.md but no LICENSE file. That is the first thing to sort out before you reuse any of this, because unknown is not the same as permissive and it is not the same as forbidden either. If you need to quote passages in internal documentation or a published article, ask the author directly, and treat the answer as the only reliable source of rights here. The manuals/ directory raises a second question. Vendored documentation from a vendor carries the vendor's terms, and a set of personal notes that embed or summarise that documentation inherits the same constraint. This is not legal advice, and it is not a problem unique to this repository, but it is the kind of thing that bites a team that copies a technical description into a design document without checking where it came from. The maintenance picture is straightforward. The repository is not archived, the last push was on 2026-06-24, and there are no GitHub releases, so there is no version to pin. The content you read on a given day is whatever is on the main branch, and the only date attached to any page is the commit that last touched it. So the checks before adopting are these. Confirm the chapter list covers the volumes you actually need, since it currently stops short of a complete manual. Confirm with the author what you may reuse. And when a specific detail matters, verify it against the manual itself, because a condensed note is a second-hand source by construction. ## Conclusion Adopt cpu-internals as a reading aid if you are learning system programming, operating system internals or virtualization and you want a short path through the Intel manual chapters that matter, with the source of each claim visible. Do not adopt it as a reference to quote from memory, because it is one person's condensed notes with an unknown licence and a coverage that stops partway through. Verify first that the chapter list matches the volume of the SDM you own, that the wording in a given section still reflects the current manual, and that the unknown licence status permits you to reuse anything you copy. ## FAQ ### What is the cpu-internals repository based on? The README states that the notes are taken from the Intel SDM, and describes them as a short or resumed version of some parts of the manuals that the author found worth looking at while learning about system programming, OS internals or virtualization. ### Which parts of the Intel manual does cpu-internals cover? The contents list covers Volume 1 chapters 3 and 6, Volume 2 chapter 6 on safer mode extensions, and twelve Volume 3 chapters covering system architecture, protected mode memory management, paging, interrupt and exception handling, cache control, debug and TSC features, architecture compatibility, and the VMX chapters 23, 24, 25, 28 and 30. ### Does cpu-internals contain runnable code or an installation step? No. The repository is documentation, with a README.md, a chapter-06-interrupt-and-exception-handling.md file, hardware.md, a VMCS-Layout.pdf and the assets, figures, headers and manuals directories. There is no build step, no package to install and no GitHub releases. ### What licence applies to cpu-internals? No licence file exists at the top level of the repository, so there is no stated permission for reuse. The README also points to a manuals directory, which raises a separate question about the terms of the vendored Intel documentation itself. ## Sources - [ayoubfaouzi/cpu-internals on GitHub](https://github.com/ayoubfaouzi/cpu-internals) - [Issues](https://github.com/ayoubfaouzi/cpu-internals/issues) - [README](https://github.com/ayoubfaouzi/cpu-internals/blob/main/README.md) --- Hysen Labs editorial analysis, written from the project's own repository and release notes. Cite the canonical page: https://hysenlabs.com/projects/ayoubfaouzi-cpu-internals