# Chisel: a Scala-embedded HDL that emits SystemVerilog through CIRCT

> Chisel is a hardware description language embedded in Scala, used to build parameterizable RTL generators for ASIC and FPGA work. It is not a woodworking tool, and its documentation is the only reliable guide to what it does.

**chipsalliance/chisel** — Chisel: A Modern Hardware Design Language

- Repository: https://github.com/chipsalliance/chisel
- Website: https://www.chisel-lang.org/
- Stars: 4,798 · Forks: 659
- Language: Scala
- License: Apache-2.0
- Published: 2026-09-23 · Updated: 2026-09-23 · Language: en
- Canonical page: https://hysenlabs.com/projects/chipsalliance-chisel

## What Chisel solves, and who it is actually for

Writing Verilog by hand does not scale when the same block has to be instantiated at a dozen widths, depths or pipeline lengths. Chisel's answer is to make the circuit a program. The README describes it as adding hardware construction primitives to Scala, so a designer writes ordinary Scala that constructs hardware, and the result is synthesizable Verilog. The stated goal is parameterizable circuit generators and design reuse across ASIC and FPGA logic.

The audience is narrower than the name suggests. If you write one-off RTL and never revisit it, Chisel adds a Scala toolchain, a build system and a compiler stage in exchange for little. If you maintain a family of related blocks, or you build a chip generator, the abstraction pays for itself. The README points to the Chisel Standard Library, which ships FIFO queues and arbiters as reusable components, as the concrete example of raising abstraction while keeping fine-grained control.

One practical warning before anything else: searching for this project is noisy. Most results for the bare word describe woodworking tools. The project lives at chisel-lang.org and in the chipsalliance/chisel repository.

## The FIRRTL and CIRCT pipeline behind a Chisel module

Chisel does not compile straight to Verilog. The README states that Chisel is powered by FIRRTL, the Flexible Intermediate Representation for RTL, a hardware compiler framework implemented by LLVM CIRCT. So the data flow is: Scala source constructs a Chisel circuit, that circuit becomes FIRRTL, and CIRCT's firtool lowers it to Verilog or SystemVerilog.

That intermediate layer is where much of the interesting behaviour lives. Because the design passes through a compiler, optimizations, width inference and lowering decisions happen after your Scala has run. The README's LED blink example shows the output header as generated by CIRCT firtool-1.37.0, which makes the dependency concrete: the emitted Verilog carries the version of the tool that produced it, not just the Chisel version.

For adopters this means the toolchain has more moving parts than a plain HDL. A Chisel version, a Scala version and a firtool version all have to agree. The repository layout reflects that, with separate top-level directories for core, firrtl, stdlib, svsim, macros, plugin and unroll, plus a build.mill file and a nix flake for reproducible environments. The split is a signal about how the project is maintained: it is a set of cooperating sub-projects, not a single monolithic compiler.

## Installing Chisel and generating your first SystemVerilog

The README does not give a standalone install command. It directs readers to Getting Started, which lists the Bootcamp interactive tutorial, a textbook, and a page titled Build Your Own Chisel Projects. The supported path is to create a project against the published artifacts rather than to install a binary.

The example below is the README's own LED blink module, reproduced as the project presents it. It imports chisel3, chisel3.util.Counter and circt.stage.ChiselStage, defines a Blinky module whose only output is a Bool, and toggles it every half period using the built-in Counter.

```scala
import chisel3._
import chisel3.util.Counter
import circt.stage.ChiselStage

class Blinky(freq: Int, startOn: Boolean = false) extends Module {
  val io = IO(new Bundle {
    val led0 = Output(Bool())
  })
  val led = RegInit(startOn.B)
  val (_, counterWrap) = Counter(true.B, freq / 2)
  when(counterWrap) {
    led := ~led
  }
  io.led0 := led
}
```

The Main object is where emission happens. The README passes the module to ChiselStage.emitSystemVerilog with two firtool options, -disable-all-randomization and -strip-debug-info, and prints the returned string. Those option names are worth noting because they change the emitted output rather than the simulation behaviour.

```scala
object Main extends App {
  println(
    ChiselStage.emitSystemVerilog(
      new Blinky(1000),
      firtoolOpts = Array("-disable-all-randomization", "-strip-debug-info")
    )
  )
}
```

What you should see is a SystemVerilog module named Blinky with clock, reset and io_led0 ports, an internal led register and a counter register, and an always block on the positive clock edge. The README shows the counter comparison against 9'h1F3 for a frequency of 1000, and the reset branch clearing both registers. If your output looks structurally different, the firtool version is the first thing to check.

## Where Chisel is the wrong tool

Chisel ties your design flow to the JVM and to a Scala build. That is a real cost for small projects. A team that wants to hand a single Verilog file to a synthesis tool, with no compiler in the loop, is better served by Verilog or SystemVerilog directly. The generator methodology is the point, and if you are not generating, you are paying for machinery you do not use.

The generated output is also not meant to be edited. The README's example output includes comments and structure produced by firtool; treating that SystemVerilog as the source of truth inverts the workflow. Any manual change is lost the next time the generator runs.

The documentation is uneven in places. The README covers what Chisel is, links to a Bootcamp, a textbook and a contributor guide, and notes that the project holds a Chisel Dev Meeting, but it does not document a rollback path or a migration procedure between major versions. The repository has a ROADMAP.md and a PROJECT_CHARTER.md, which is more governance detail than many projects provide, yet version selection is handled by a single README section titled Which version should I use? That is thin for a language where the emitted Verilog depends on the compiler version. Anyone planning a long-lived design should expect to pin versions deliberately and to re-verify output after an upgrade, because the README does not promise output stability across releases.

## Chisel against plain Verilog and against high-level synthesis

The closest comparison is hand-written Verilog or SystemVerilog. The difference is not syntax, it is where parameterization lives. In Verilog you use parameters, generate blocks and macros; in Chisel you use Scala functions, classes and the type system, and the elaboration runs as a program. The README frames this as advanced circuit generation and design reuse, and points to a Stack Overflow answer titled What benefits does Chisel offer over classic Hardware Description Languages? rather than arguing the case inline. That is honest: the project treats the comparison as a settled question and links out.

A second alternative is high-level synthesis from C or C++. HLS typically starts from an algorithmic description and infers a microarchitecture under constraints. Chisel does not infer a microarchitecture. You describe registers, wires and combinational logic explicitly at the register-transfer level, and the compiler lowers that description. The README is explicit that Chisel describes digital electronics at the register-transfer level. If your team wants to write an algorithm and let a tool schedule it, Chisel is the wrong abstraction. If you want explicit control over cycles and state, the generator approach fits better than HLS scheduling heuristics.

## Licence, releases and what an upgrade actually costs

Chisel is licensed under Apache 2.0, described in the README as permissively licensed and developed under the guidance of CHIPS Alliance. For most commercial RTL work that is a permissive arrangement, but the licence text in LICENSE is the authority, and the usual Apache 2.0 obligations around notices and attribution still apply. Nothing here is legal advice; read LICENSE before shipping.

Release cadence is visible in the tags. v7.13.0 appeared on 2026-06-01, v7.14.0 on 2026-08-13, and v7.15.0 on 2026-09-01, with the last push to the repository on 2026-09-22. That is a steady stream of minor releases rather than long-term support branches, and the README does not describe an LTS line. The practical consequence is that an upgrade is not a version bump you can ignore: because the emitted Verilog is produced by CIRCT firtool, a new Chisel release can change the generated RTL. Budget time to regenerate and diff your output, not just to update a dependency.

The repository also carries a .scala-steward.conf file, which indicates automated dependency update pull requests, and a .mergify.yml for merge automation. Both suggest the project expects frequent dependency movement. If you pin Chisel in a long-running design, expect to revisit that pin deliberately.

## Conclusion

Adopt Chisel if your design work is dominated by parameterized, reused blocks and your team already writes Scala or is willing to learn it. Do not adopt it if you need a small, self-contained language with no JVM or build toolchain, or if your flow depends on hand-written Verilog you intend to edit. Before committing, verify which Chisel version your project should target, confirm that firtool is available for your platform, and check that your downstream synthesis and simulation tools accept the SystemVerilog that ChiselStage.emitSystemVerilog produces.

## FAQ

### What is Chisel used for?

Chisel is an open-source hardware description language used to describe digital electronics and circuits at the register-transfer level, for both ASIC and FPGA designs. It adds hardware construction primitives to Scala so designers can write parameterizable circuit generators that produce synthesizable Verilog.

### How do I install Chisel?

The README does not give a standalone install command. It points to Getting Started, which offers a Bootcamp interactive tutorial, a textbook, and a page called Build Your Own Chisel Projects, so the supported route is to set up a project against the published artifacts rather than install a binary.

### How do I use Chisel to generate Verilog?

You define a Module in Scala and pass it to ChiselStage.emitSystemVerilog, as the README's Blinky example does with firtoolOpts set to -disable-all-randomization and -strip-debug-info. The returned string is the generated SystemVerilog, which the README prints.

### Are the search results for Chisel about this project?

Mostly not. The bare word usually refers to woodworking tools, masonry chisels, chisel tip markers or Minecraft mods. The hardware project is at chisel-lang.org and in the chipsalliance/chisel repository.

### What does Chisel compile through before producing Verilog?

The README states that Chisel is powered by FIRRTL, a hardware compiler framework implemented by LLVM CIRCT. The generated Verilog in the README carries a header naming the CIRCT firtool version that produced it.

### What licence is Chisel released under?

Chisel is permissively licensed under Apache 2.0, under the guidance of CHIPS Alliance, according to the README. The LICENSE file in the repository is the authoritative text.

## Sources

- [chipsalliance/chisel on GitHub](https://github.com/chipsalliance/chisel)
- [License: Apache-2.0](https://github.com/chipsalliance/chisel/blob/main/LICENSE)
- [Project website](https://www.chisel-lang.org/)
- [README](https://github.com/chipsalliance/chisel/blob/main/README.md)
- [Releases](https://github.com/chipsalliance/chisel/releases)

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Hysen Labs editorial analysis, written from the project's own repository and release notes. Cite the canonical page: https://hysenlabs.com/projects/chipsalliance-chisel