pulp-platform
★ 1,734axi
AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
HYSEN LABS DIRECTORY
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AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
Common SystemVerilog components
The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core