Ibex: a parametrizable 32-bit RISC-V CPU core in SystemVerilog, with tape-out verification

Ibex is a parametrizable 32-bit RISC-V core for embedded control, not a complete SoC

Ibex is a CPU core in isolation: a 32-bit RISC-V implementation written in SystemVerilog and designed for embedded control applications. It is not a system-on-chip and does not include a memory subsystem, peripheral controllers, or an interconnect fabric. Those pieces come from the integration layer, and Ibex provides the processor at the center.

The project was originally developed under the name "Zero-riscy" as part of the PULP platform and was contributed to lowRISC, which now maintains it. It has seen multiple tape-outs, and the readme states it is under active development. A nightly regression report for the OpenTitan configuration is linked at the top of the readme, showing Ibex's role in that project.

Supported ISA extensions are the Integer (I) or Embedded (E), Integer Multiplication and Division (M), Compressed (C), and B (Bit Manipulation) extensions. For bit manipulation specifically, the ratified v.1.0.0 RISC-V Bit-Manipulation Extension covers Zba, Zbb, Zbc and Zbs, along with the Zbkb and Zbkx sub-extensions from the RISC-V Scalar Cryptography Extension.

Four named configurations span from 16.85 kGE to 66.02 kGE in Yosys area

The readme documents four configurations: micro, small, maxperf and maxperf-pmp-bmfull. Each is characterized by its ISA, multiplier pipeline, optional micro-architecture features, area in kGE and CoreMark/MHz score on the Ibex Simple System platform.

The micro configuration targets RV32EC with an area of 16.85 kGE under Yosys synthesis, and an estimated commercial synthesis area of around 15 kGE. Its CoreMark/MHz score is 0.904.

The small configuration adds RV32IMC with a 3-cycle multiplier, reaching 26.60 kGE in Yosys and a CoreMark/MHz of 2.47. This is the default configuration in the Makefile, where `IBEX_CONFIG ?= small` is set.

The maxperf configuration uses RV32IMC with a 1-cycle multiplier, a branch target ALU and a writeback stage, reaching 32.48 kGE and 3.13 CoreMark/MHz. The maxperf-pmp-bmfull configuration adds RV32IMCB, 16 PMP regions, and the same micro-architecture features as maxperf, reaching 66.02 kGE in Yosys at the same 3.13 CoreMark/MHz.

Commercial synthesis area estimates are noted as rough figures: approximately 15, 24, 30 and 61 kGE for the four configurations respectively.

The micro configuration carries Red verification status: minimal or no verification performed

The readme assigns a verification status to each configuration. Green indicates that verification is close to complete. Amber means some verification has been performed but the configuration is still experimental. Red means minimal or no verification.

Of the four named configurations, micro is Red. Small, maxperf and maxperf-pmp-bmfull are all Green. An explicit caution appears in the readme: "Users must make their own assessment of verification readiness for any tapeout."

Two distinctions matter here. First, Green does not mean complete. "Close to complete" is the stated description, which leaves final verification steps for the adopting team. Second, micro is documented in ibex_configs.yaml as a supported configuration, yet its Red status means it requires substantial additional verification before any tapeout use.

For comparison, the original Zero-riscy core yields an area of 23.14 kGE under the same Yosys synthesis flow, sitting between the small and maxperf configurations by area.

Building the Simple System simulation target with FuseSoC and the Makefile

The repository's Makefile provides shorthand targets for common tasks. The help target explicitly redirects to the documentation for setup and environment instructions, so the full getting-started path lives at ibex-core.readthedocs.io rather than in the Makefile itself.

For a simulation run against the Simple System, the Makefile defines a build target and a run target. Building the simulation binary:

make build-simple-system

After the binary is built, the run-simple-system target compiles a bare metal hello_test binary and executes the simulation against it. Underneath both targets is a FuseSoC invocation that resolves the core dependencies and drives the build. FuseSoC is the package manager and build tool the project uses throughout.

Simple System targets simulation only and is intentionally minimal. For an FPGA target with a debug interface, the Ibex Demo System is the more complete example, maintained in a separate repository.

maxperf-pmp-bmfull matches maxperf at 3.13 CoreMark/MHz while nearly doubling in area

Both maxperf and maxperf-pmp-bmfull score 3.13 CoreMark/MHz, yet their areas differ sharply. maxperf reaches 32.48 kGE in Yosys synthesis; maxperf-pmp-bmfull reaches 66.02 kGE. Commercial synthesis estimates follow the same ratio: approximately 30 kGE versus approximately 61 kGE.

The area increase comes from adding RV32IMCB (bit manipulation) and 16 Physical Memory Protection (PMP) regions on top of the maxperf base. The CoreMark benchmark does not exercise either of those features directly, which is why the score is unchanged.

A team deciding between these two configurations is choosing between PMP-enforced memory protection and bit manipulation instruction support on one side and roughly half the silicon area on the other. The CoreMark score alone does not capture that trade-off, and the readme notes that different ISAs give the best results for different configurations depending on which extensions are exercised.

Performance numbers are based on CoreMark running on the Ibex Simple System platform.

The Ibex Demo System targets the Arty A7 FPGA with OpenOCD and GDB over USB

Beyond the in-repository Simple System, a more complete integration example exists as a separate repository at github.com/lowrisc/ibex-demo-system. It is maintained by lowRISC but is not an official part of Ibex itself.

The Demo System targets the Arty A7 FPGA board from Digilent and integrates the PULP RISC-V debug module. Debugging is via OpenOCD and GDB over USB, with no external JTAG probe required. This is the significant practical detail: the Arty A7 exposes its JTAG interface through the onboard USB connection, so the demo environment does not require additional hardware beyond the board itself.

The README for the Simple System inside the repository describes an intentionally minimal integration aimed at simulation, while the Demo System adds the peripherals, board connections and debug infrastructure needed to run on physical hardware. The two serve different purposes, and the README guides the reader to the appropriate one based on the goal.

lowRISC CLA applies to all contributions, and Apache-2.0 covers the repository

Contributing to Ibex requires signing the lowRISC Contributor License Agreement at CLA.md before pull requests are accepted. SystemVerilog source code contributions follow the lowRISC Verilog coding style guide. C and C++ contributions follow the OpenTitan C++ coding style guide, and C/C++ files must be formatted with clang-format before committing, either by running `clang-format -i filename.cc` or `git clang-format` on added files.

Apache License, Version 2.0 covers this repository (full text in LICENSE), and the last push was on 2026-10-06 with no GitHub releases. Questions go to the public Ibex channel on Zulip at lowrisc.zulipchat.com.

Editorial conclusion

Ibex is the right choice when you need a parametrizable 32-bit RISC-V core for an embedded application, specifically the small or maxperf configuration where verification is close to complete. The micro configuration carries Red verification status and is not appropriate for tapeout without additional verification work by the adopting team. The identical CoreMark/MHz scores for maxperf and maxperf-pmp-bmfull hide a near-doubling of area, so the choice between them depends on whether PMP regions and bit manipulation are required. Before integrating, read the verification status notes in ibex_configs.yaml and the full documentation at ibex-core.readthedocs.io, because the README is a summary and configuration details live there.

Frequently asked questions

Official sources

1. Issues
2. License: Apache-2.0
3. lowRISC/ibex on GitHub
4. Project website
5. README