VexRiscv: A Plugin-Configurable 32-bit RISC-V CPU Core for FPGAs

What VexRiscv Is For and Who Uses It

VexRiscv targets FPGA engineers who want a 32-bit RISC-V processor they can synthesize onto commodity FPGAs without paying licensing fees or relying on vendor-specific IP blocks. The CPU description language is SpinalHDL, a Scala-based hardware description language that generates Verilog or VHDL. This means the CPU is defined in software and the output is a hardware description file that flows through standard FPGA synthesis tools.

The project supports AXI4, Avalon, and Wishbone bus protocols, which makes it compatible with a wide range of SoC infrastructure components. It runs Linux through the linux-on-litex-vexriscv project, runs Zephyr, and a FreeRTOS port is maintained separately. These operating system targets make it practical for applications that need a real software stack above the hardware.

The README identifies no specific category of end-user beyond FPGA engineers who need a configurable soft CPU. The commercial support contact suggests it is used in production FPGA products as well as in research and education.

The Plugin Architecture and What It Controls

Nearly every functional element in VexRiscv is a plugin. The pipeline stage count, the branch predictor, the register file implementation, the hazard controller, the instruction cache, the data cache, the MMU, the FPU, the multiplier and divider, and the debug interface are all separate plugin modules that compose into the final CPU configuration.

Plugins can insert data into the pipeline at one stage and read it in another stage through automatic pipeline forwarding. The README describes a service system where one plugin can declare a capability (such as an exception service) that other plugins use to emit exceptions from the pipeline, without any plugin needing to know the full set of other plugins present.

This architecture means the CPU has a very small fixed core. The README publishes synthesis results for several configurations. The minimal RV32I build with no datapath bypass and no interrupt support produces:

VexRiscv small (RV32I, 0.52 DMIPS/MHz, no datapath bypass, no interrupt) ->
    Artix 7     -> 243 MHz 504 LUT 505 FF
    Cyclone V   -> 174 MHz 352 ALMs
    Cyclone IV  -> 179 MHz 731 LUT 494 FF
    iCE40       -> 92 MHz 1130 LC

A full configuration that enables five pipeline stages, instruction and data caches, a hardware multiplier and divider, dynamic branch prediction, and an FPU reaches 1.44 DMIPS/MHz on the dhrystone benchmark, compiled with -O3 -fno-inline.

The README notes that the small configurations benefit from an optional removal of the Fetch, Memory, and WriteBack stages, which reduces area while improving DMIPS/MHz for the simplified pipeline.

Supported Instruction Set Extensions and Bus Interfaces

The instruction set support follows the RISC-V standard extension naming convention. The supported set is RV32I[M][A][F[D]][C], meaning the base integer instruction set is always present, with optional integer multiplication and division (M), atomic instructions (A), single-precision floating-point (F), double-precision floating-point (D), and compressed instructions (C). The FPU requires the data cache to be enabled.

Branch prediction is available in four modes: no prediction, static prediction, dynamic prediction using a counter, and dynamic prediction with a direct-mapped target buffer cache that eliminates penalties on correct predictions. The README notes that dynamic branch prediction with a target buffer cache is the mode used in the highest-performance configuration.

The CPU supports Machine, Supervisor, and User privilege levels as defined in the RISC-V Privileged ISA Specification version 1.10. Optional physical memory protection is available through the PmpPlugin and PmpPluginNapot. A hardware memory management unit is available through MmuPlugin for configurations that need virtual memory, which is required for running Linux.

The debug interface uses JTAG and connects to the host via GDB through OpenOCD. The README includes instructions for interactive debugging of the simulated CPU using GDB, OpenOCD, and Verilator, and for Eclipse-based debug sessions using either the gnu-mcu-eclipse or Zylin plugin.

Building the CPU and the Dependency Chain

VexRiscv uses sbt (Scala Build Tool) for its build system. The build.sbt and build.sc files at the repository root define the project dependencies, including the SpinalHDL framework. Running sbt generates the Verilog or VHDL output for a specific CPU configuration. The demo configurations in src/scala/vexriscv/demo/ are the starting point for common use cases.

The toolchain requires Java and Scala. The README notes Ubuntu 14 as a test environment for the dependency installation steps. Verilator is needed for simulation and regression testing. The RISC-V GCC toolchain is required for compiling software that runs on the generated CPU.

The README includes a section on regression tests and a section on building the RISC-V GCC toolchain, both of which indicate the project expects users to run simulation-based verification before moving to hardware. Two complete reference SoC designs, Briey SoC and Murax SoC, demonstrate the CPU integrated with memory controllers, UART, and other peripherals.

Where VexRiscv Has Constraints

The dependency on SpinalHDL and sbt is a non-trivial adoption barrier for engineers whose teams use Verilog or VHDL directly without Scala tooling. The generated Verilog is synthesizable, but the source description is in Scala, which means modifying the CPU architecture requires understanding both SpinalHDL and the plugin composition model.

The FPU requires the data cache to be enabled. Teams building configurations with floating-point that cannot afford the area of a data cache cannot use the FPU plugin. The README does not document this constraint as resolved.

VexRiscv targets 32-bit RISC-V. There is no 64-bit variant. Projects that need RV64 need a different core.

The README itself points to VexiiRiscv (https://github.com/SpinalHDL/VexiiRiscv) as a project that readers might prefer. VexiiRiscv is presented as a newer design, suggesting VexRiscv may be approaching a maintenance-only phase for some use cases. The last push to VexRiscv was September 24, 2026, so active development continues.

Comparison with PicoRV32 and License

PicoRV32 is another FPGA-oriented RISC-V soft CPU, written in plain Verilog, targeting minimal area and straightforward integration for engineers who do not want a high-level hardware description language in their toolchain. The README's related search data mentions a comparison between VexRiscv and PicoRV32.

PicoRV32 is a simpler core with no pipelining option beyond a basic structure, no cache infrastructure, and no hardware MMU. It is easier to integrate into existing Verilog workflows and has a smaller dependency chain. VexRiscv supports a far wider feature range and reaches significantly higher DMIPS/MHz in its pipelined configurations, but it requires Scala and SpinalHDL.

For projects where the full Linux-capable, MMU-enabled, cached pipeline matters, VexRiscv provides a complete path. For projects where raw simplicity and plain Verilog source code matter more than peak performance, PicoRV32 is the lower-friction option.

VexRiscv is released under the MIT license, which allows use in commercial FPGA products without license fee obligations. The repository has no GitHub releases; the HEAD of the master branch is the reference implementation.

Editorial conclusion

VexRiscv is a well-suited choice for FPGA engineers who want a 32-bit RISC-V core they can scale from a minimal 504-LUT configuration to a Linux-capable five-stage pipeline by selecting plugins, and who are comfortable working with SpinalHDL and sbt. It is not the right option if you need a fully synthesized, pre-verified RTL drop-in for a specific silicon process node, or if your team cannot adopt Scala tooling. Before starting, check whether VexiiRiscv (mentioned in the README as a potential successor) fits your requirements better, and verify that your target FPGA vendor's tools accept the generated Verilog from SpinalHDL.

Frequently asked questions

Official sources

1. Issues
2. License: MIT
3. README
4. SpinalHDL/VexRiscv on GitHub